HD6433308 Datasheet, PDF (154/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

(1) Upper byte read
CPU writes
data H’AA
Bus interface
(2) Lower byte read
Module data bus
TEMP
[H’55]
FRC H
[H’AA]
FRC L
[H’55]
CPU writes
data H’55
Bus interface
Module data bus
TEMP
[H’55]
FRC H
[]
FRC L
[]
Figure 6-4 (b). Read Access to FRC (When FRC Contains H’AA55)
6.4 Operation
6.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
The internal clock sources are created from the system clock (Ø) by a prescaler. The FRC
increments on a pulse generated from the falling edge of the prescaler output. See Figure 6-5.
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