HD6433308 Datasheet, PDF (182/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Write cycle: CPU writes to TCORA or TCORB
T1
T2
T3
Ø
Internal address
bus
Internal write
signal
TCOR address
TCNT
N
N+1
TCORA or
TCORB
Compare-match
A or B signal
N
M
TCOR write data
Inhibited
Figure 7-15. Contention between TCOR Write and Compare-Match
(4) Contention between Compare-Match A and Compare-Ma^Ftc^igh^urB^e:^7-I¹f⁵identical time constants
are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any
conflict between the output selections for compare-match A and B is resolved by following the
priority order in Table 7-4.
Table 7-4. Priority of Timer Output
Output selection
Toggle
“1” Output
“0” Output
No change
Priority
High
Low
(5) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the timer counter to increment. This depends on the
time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in Table 7-5.
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