HD6433308 Datasheet, PDF (148/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 4
ICFD
0
1
Description
To clear ICFD, the CPU must read ICFD after it
has been set to "1," then write a “0” in this bit.
This bit is set to 1 when an FTID input signal is received.
(Initial value)
Bit 3 – Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 3
OCFA
0
1
Description
To clear OCFA, the CPU must read OCFA after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC = OCRA.
(Initial value)
Bit 2 – Output Compare Flag B (OCFB): This status flag is set to “1” when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2
OCFB
0
1
Description
To clear OCFB, the CPU must read OCFB after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC = OCRB.
(Initial value)
Bit 1 – Timer Overflow Flag (OVF): This status flag is set to “1” when the FRC overflows
(changes from H’FFFF to H’0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
0
1
Description
To clear OVF, the CPU must read OVF after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC changes from H’FFFF to H’0000.
(Initial value)
133