HD6433308 Datasheet, PDF (244/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 4
EAKAR
0
1
Description
RDY output is disabled. RDY remains in the high-impedance state.
RDY output is enabled.
(Initial state)
Bit 3 – Master Read End Flag (MREF): This flag indicates whether the master CPU has finished
reading data set in the parallel communication data registers.
Bit 3
MREF
0
1
Description
This bit is cleared to “0” when:
• The H8/300 CPU reads or writes PCDR0.
• The master CPU writes to PCDR0.
This bit is set to “1” when the master CPU reads PCDR0.
(Initial state)
Bit 2 – Enable Master Read Interrupt (EMRI): This bit enables or disables the master read end
interrupt (MREI).
Bit 2
EMRI
0
1
Description
The master read end interrupt request (MREI) is disabled.
The master read end interrupt request (MREI) is enabled.
(Initial state)
Bit 1 – Master Write Mode Flag (MWMF): This bit indicates when the dual-port RAM is in the
master write mode. The master CPU should check that this bit is set to “1” before writing to
parallel communication data registers 1 to 14. The H8/300 CPU cannot write in those registers
while this bit is set to “1.”
Bit 1
MWMF
0
1
Description
This bit is cleared to “0” when the H8/300 CPU reads PCDR0.
The dual-port RAM is not in the master write mode. The master
CPU should avoid writing in PCDR1 to PCDR14.
This bit is set to “1” if the master CPU writes to PCDR0 while the
SWMF flag is cleared to “0.” The dual-port RAM is in the master
write mode. Only the master CPU can write in PCDR1 to PCDR14.
(Initial state)
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