HD6433308 Datasheet, PDF (160/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

(3) Timing of Input Capture Flag (ICF) Clearing: The input capture flag ICFx (x = A, B, C, D)
is cleared when the CPU writes a “0” in this bit.
Write cycle: CPU writes "0" in ICFx
T1
T2
T3
Ø
ICFx
Figure 6-17. Clearing of Input Capture Flag
6.4.4 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H’FFFF to
Figure 6-17
H’0000). Figure 6-18 shows the timing of this operation.
Ø
FRC
H'FFFF
H'0000
Internal overflow
signal
OVF
Figure 6-18. Setting of Overflow Flag (OVF)
(2) Timing of Overflow Flag (OVF) Clearing: The overflow flag is cleared when the CPU
writes a “0” in this bit.
Write cycle: CPU writes "0" in OVF
T1
T2
T3
Ø
OVF
Figure 6-19. Clearing of Overflow Flag
145