HD6433308 Datasheet, PDF (286/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

17.3 MCU Operational Timing
This section provides the following timing charts:
17.3.1 Bus Timing
17.3.2 Control Signal Timing
17.3.3 16-Bit Free-Running Timer Timing
17.3.4 8-Bit Timer Timing
17.3.5 PWM Timer Timing
17.3.6 SCI Timing
17.3.7 I/O Port Timing
17.3.8 Dual-port RAM Timing
Figures 17-4 to 17-6
Figures 17-7 to 17-10
Figures 17-11 to 17-12
Figures 17-13 to 17-15
Figure 17-16
Figures 17-17 to 17-18
Figure 17-19
Figures 17-20 to 17-21
17.3.1 Bus Timing
(1) Basic Bus Cycle (Without Wait States) in Expanded Modes
Ø
A15 to A0
IOS
AS, RD
(Read)
D7 to D0
(Read)
WR
D7 to D0
(Write)
T1
t cyc
t CH
tCL
t AD
t Cf
T2
t Cr
t ASD
t ASI
t _ACC
t _AS2
t WSD
tWDD
t WDS
T3
t _SD
t AH
tRDS
tRDH
tWSW
t _SD
t AH
t _WDH
Figure 17-4. Basic Bus Cycle (Without Wait States) in Expanded Modes
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