HD6433308 Datasheet, PDF (239/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 11-2. Dual-Port RAM Register Configuration (cont.)
Read/write
H8/300 Master Initial On-chip External address
Name
Abbr. CPU CPU value address RS3 RS2 RS1 RS0
Parallel communication PCDR4 R/W R/W Undeter- H’FFF5 0 1 0 1
data register 4
mined
Parallel communication PCDR5 R/W R/W Undeter- H’FFF6 0 1 1 0
data register 5
mined
Parallel communication PCDR6 R/W R/W Undeter- H’FFF7 0 1 1 1
data register 6
mined
Parallel communication PCDR7 R/W R/W Undeter- H’FFF8 1 0 0 0
data register 7
mined
Parallel communication PCDR8 R/W R/W Undeter- H’FFF9 1 0 0 1
data register 8
mined
Parallel communication PCDR9 R/W R/W Undeter- H’FFFA 1 0 1 0
data register 9
mined
Parallel communication PCDR10 R/W R/W Undeter- H’FFFB 1 0 1 1
data register 10
mined
Parallel communication PCDR11 R/W R/W Undeter- H’FFFC 1 1 0 0
data register 11
mined
Parallel communication PCDR12 R/W R/W Undeter- H’FFFD 1 1 0 1
data register 12
mined
Parallel communication PCDR13 R/W R/W Undeter- H’FFFE 1 1 1 0
data register 13
mined
Parallel communication PCDR14 R/W R/W Undeter- H’FFFF 1 1 1 1
data register 14
mined
Note: The H8/300 CPU can write only bits 6, 4, and 2 of the PCCSR. The master CPU can write
only bit 4.
11.2 Register Descriptions
11.2.1 Dual Port RAM Enable Bit (DPME)
The dual-port RAM is enabled or disabled by the DPRAM Enable (DPME) bit in the system
control register (SYSCR). In the extended modes the dual-port RAM is always disabled. In the
single-chip mode, the dual-port RAM is initially disabled but can be enabled by setting the DPME
bit to "1."
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