HD6433308 Datasheet, PDF (152/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 2 – Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB). When output compare B is disabled, the corresponding pin is used as a general-
purpose input/output or interrupt port.
Bit 2
OEB Description
0 Output compare B output is disabled.
1 Output compare B output is enabled.
(Initial value)
Bit 1 – Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 1
OLVLA
0
1
Description
A “0” logic level (Low) is output for compare-match A.
A “1” logic level (High) is output for compare-match A.
(Initial value)
Bit 0 – Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
Bit 0
OLVLB
0
1
Description
A “0” logic level (Low) is output for compare-match B.
A “1” logic level (High) is output for compare-match B.
(Initial value)
6.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When
the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the
access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when
the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16
bits are written in the register simultaneously.
137