HD6433308 Datasheet, PDF (339/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

SSR—Serial Status Register
H’FFDC
SCI
Bit
7
6
5
4
3
2
1
0
TDRE RDRF ORER FER PER
—
—
—
Initial value 1
0
0
0
0
1
1
1
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* —
—
—
Parity Error
0 Cleared when CPU reads PER = “1,” then
writes “0” in PER.
1 Set when a parity error occurs (parity of receive
data does not match parity selected by O/E bit).
Framing Error
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
1 Set when a framing error occurs (stop bit is “0”).
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely
received while RDRF bit is set to “1”).
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1 Set when one character is received normally and transferred from
RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = "0."
* Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
RDR—Receive Data Register
Bit
7
6
5
Initial value 0
0
0
Read/Write R
R
R
H’FFDD
4
3
2
0
0
0
R
R
R
Receive data
SCI
1
0
0
0
R
R
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