HD6433308 Datasheet, PDF (233/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

In the scan mode, the ranges given in table 10-4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = "0") or 128 states
(when CKS = "1").
(1)
Ø
Internal address bus
(2)
Write signal
Input sampling timing
ADF
tD
t SPL
(Notation)
(1) ADCSR write cycle
(2) ADCSR address
tD
Synchronization delay
tSPL Input sampling time
tCONV Total A/D conversion time
t CONV
Figure 10-5. A/D Conversion Timing
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