HD6433308 Datasheet, PDF (158/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

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Input at FTI pin
Internal input
capture signal
Figure 6-12. Input Capture Timing (Usual Case)
If the upper byte of ICRx is being read when the input capture signal arrives, the internal input
capture signal is delayed by one state. Figure 6-13 shows the timing for this case.
Read cycle: CPU reads upper byte of ICR
T1
T2
T3
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-13. Input Capture Timing (1-State Delay)
In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned. When
ICRA and ICRC are used in buffer mode, for example, if the upper byte of either ICRA or ICRC is
being read when the FTIA input arrives, the internal input capture signal is delayed by one state.
Figure 6-14 shows the timing for this case. The case of ICRB and ICRD is simila^Fr^ig. ^{ure 6-13}
Read cycle: CPU reads upper byte of ICRA or ICRC
T1
T2
T3
Ø
Input at
FTIA pin
Internal input
capture signal
Figure 6-14. Input Capture Timing (1-State Delay, Buffer Mode)
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Figure 6-14