HD6433308 Datasheet, PDF (130/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Port 9 Data Direction Register (P9DDR)—H’FFC0
Bit
7
6
5
4
3
2
1
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value
0
1
0
0
0
0
0
0
Read/Write
W
—
W
W
W
W
W
W
Mode 3
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an
output pin if the corresponding bit in P9DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Port 9 Data Register (P9DR)—H’FFC1
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
P9DR is an 8-bit register containing the data for pins P97 to P90. When the CPU reads P9DR, for
output pins (P9DDR = "1") it reads the value in the P9DR latch, but for input pins (P9DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P9DR latch. This also applies to pins
used for interrupt input, A/D trigger input, clock output, and control signal input or output.
MOS Pull-Ups: Are available for input pins, including pins used for input of interrupt request
signals, the A/D trigger signal, and control signals. Software can turn the MOS pull-up on by
writing a “1” in P9DR, and turn it off by writing a “0.”
Pins P90, P91, and P92: Can be used for general-purpose input or output, interrupt request input,
or A/D trigger input. See Table 5-18. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to "0," so that the output from P9DR will not generate an interrupt
request or A/D trigger signal.
Pins P93 and P94: In modes 1 and 2 (the expanded modes), these pins are used for output of the
RD and WR bus control signals. They are unaffected by the values in P9DDR and P9DR, and their
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