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HD6433308 Datasheet, PDF (210/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer | |||
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 The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated
format as follows.
i) Start bit (one â0â bit).
ii) Transmit data (seven or eight bits, starting from bit 0)
iii) Parity bit (odd or even parity bit, or no parity bit)
iv) Stop bit (one or two consecutive â1â bits)
 Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit
is set to â1.â
If the TIE bit is set to â1,â a transmit-end interrupt (TxI) is requested.
When the transmit function is enabled but the TDR is empty (TDRE = â1â), the output at the
ATxD pin is held at â1â until the TDRE bit is cleared to â0.â
* A frame is the data for one character, including the start bit and stop bit(s).
⢠Data Reception: The procedure for receiving data is as follows.
 Set up the desired receiving conditions in the SMR, SCR, and BRR.
 Set the RE bit in the SCR to â1.â
The ARxD pin is automatically be switched to input and the SCI is ready to receive data.
 The SCI synchronizes with the incoming data by detecting the start bit, and places the received
bits in the RSR. At the end of the data, the SCI checks that the stop bit is â1.â
 When a complete frame has been received, the SCI transfers the received data from the RSR to
the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the
RDR is cleared to â0.â
At the same time, the SCI sets the RDRF bit in the SSR to â1.â If the RIE bit is set to â1,â a
receive-end interrupt (RxI) is requested.
 The RDRF bit is cleared to â0â when software reads the SSR, then writes a â0â in the RDRF bit.
The RDR is then ready to receive the next character from the RSR.
When a frame is not received correctly, a receive error occurs. There are three types of receive
errors, listed in Table 9-8.
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