HD6433308 Datasheet, PDF (149/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 0 – Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
0
The FRC is not cleared.
1
The FRC is cleared at compare-match A.
(Initial value)
6.2.6 Timer Control Register (TCR) – H’FF96
Bit
Initial value
Read/Write
7
6
5
4
3
2
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 7
IEDGA
0
1
Description
Input capture A events are recognized on the falling edge of FTIA.
Input capture A events are recognized on the rising edge of FTIA.
(Initial value)
Bit 6 – Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 6
IEDGB
0
1
Description
Input capture B events are recognized on the falling edge of FTIB.
Input capture B events are recognized on the rising edge of FTIB.
(Initial value)
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