HD6433308 Datasheet, PDF (55/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

3.5.3 Logic Operations
Table 3-4 describes the four instructions that perform logic operations. See figure 3-6 in section
3.5.4, “Shift Operations” for their object codes.
Table 3-4. Logic Operation Instructions
Instruction
AND
OR
XOR
NOT
Size*
B
B
B
B
Function
Rd ∧ Rs → Rd, Rd ∧ #imm → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #imm → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #imm → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ (Rd) → (Rd)
Obtains the one’s complement (logical complement) of general register
contents.
3.5.4 Shift Operations
Table 3-5 describes the eight shift instructions. Figure 3-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 3-5. Shift Instructions
Instruction
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Size*
B
B
B
B
Function
Rd shift → Rd
Performs an arithmetic shift operation on general register contents.
Rd shift → Rd
Performs a logical shift operation on general register contents.
Rd rotate → Rd
Rotates general register contents.
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit.
* Size: operand size
B: Byte
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