HD6433308 Datasheet, PDF (218/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Basic clock
Receive data
0 1 2 3 4 5 6 7 8 9 1011121314 1516 1 2 3 4 5 6 7 8 9 10 11 12131415 16 1 2 3 4 5
–7.5 pulses
+7.5 pulses
Start bit
D0
D1
Sync sampling
Data sampling
Figure 9-6. Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] (1)
M: Receive margin
N: Ratio of basic clock to baud rate (N=16)
D: Duty factor of clock—ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F= 0
M = (0.5 –1/2 × 16) × 100 [%] = 46.875%
(2)
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