HD6433308 Datasheet, PDF (151/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 1
CKS1
0
0
1
1
Bit 0
CKS0
0
1
0
1
Description
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
(Initial value)
6.2.7 Timer Output Compare Control Register (TOCR) – H’FF97
Bit
7
6
5
4
3
2
1
0
—
—
— OCRS OEA OEB OLVLA OLVLB
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
— R/W R/W R/W R/W R/W
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H’E0 at a reset and in the standby modes.
Bits 7 to 5 – Reserved: These bits cannot be modified and are always read as “1.”
Bit 4 – Output Compare Register Select (OCRS): When the CPU accesses addresses H’FF94
and H’FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H’FF94
Lower byte of OCRA and lower byte of OCRB: H’FF95
Bit 4
OCRS
0
1
Description
The CPU can access OCRA.
The CPU can access OCRB.
(Initial value)
Bit 3 – Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA). When output compare A is disabled, the corresponding pin is used as a general-
purpose input/output port.
Bit 3
OEA
0
1
Description
Output compare A output is disabled.
Output compare A output is enabled.
(Initial value)
136