HD6433308 Datasheet, PDF (143/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown
in Figure 6-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and
the new FRC count is copied into ICRA.
BUFEA
IEDGA IEDGC
FTIA
Edge detect and
capture signal
generating circuit
ICRC
ICRA
FRC
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Buffer Enable A
Input Edge Select A
Input Edge Select C
Input Capture Register C
Input Capture Register A
Free-Running Counter
Figure 6-2. Input Capture Buffering
Similarly, when the BUFEB bit in TIER is set to “1,” ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See Section 6.3, “CPU Interface” for details.
To ensure input capture, the width of the input capture pulse (FTIA, FTIB, FTIC, FTID) should be
at least 1.5 system clock periods (1.5·Ø). When triggering is enabled on both edges, the input
capture pulse width should be at least 2.5 system clock periods.
Ø
FTIA, FTIB,
FTIC, or FTID
Figure 6-3. Minimum Input Capture Pulse Width
128