HD6433308 Datasheet, PDF (317/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

TIER—Timer Interrupt Enable Register
H’FF90
FRT
Bit
7
6
5
4
3
2
1
0
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE —
Initial value 0
0
0
0
0
0
0
1
Read/Write R/W R/W R/W R/W R/W R/W R/W —
Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0 Output compare interrupt request B is disabled.
1 Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0 Output compare interrupt request A is disabled.
1 Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0 Input capture interrupt request D is disabled.
1 Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0 Input capture interrupt request C is disabled.
1 Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0 Input capture interrupt request B is disabled.
1 Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0 Input capture interrupt request A is disabled.
1 Input capture interrupt request A is enabled.
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