HD6433308 Datasheet, PDF (234/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 10-4 (a). A/D Conversion Time (Single Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time
Symbol
tD
tSPL
tCONV
CKS = "0"
min typ max
18 — 33
— 63 —
227 — 242
CKS = "1"
min typ max
10
—
17
—
31
—
115 —
122
Table 10-4 (b). A/D Conversion Time (Scan Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time
Symbol
tD
tSPL
tCONV
CKS = "0"
min typ max
18 — 33
— 63 —
259 — 274
CKS = "1"
min typ max
10
—
17
—
31
—
131 —
138
Note: Values in the tables above are numbers of states.
10.3.4 External Trigger Input Timing
A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled or
disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to "1," when
a falling edge of ADTRG is detected the ADST bit is set to "1" and A/D conversion begins.
Subsequent operation is the same as when the ADST bit is set to "1" by software.
Figure 10-6 shows the trigger timing.
Ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 10-6. External Trigger Input Timing
222