HD6433308 Datasheet, PDF (223/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The ADCSR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF
0
1
Description
To clear ADF, the CPU must read ADF after
it has been set to "1," then write a "0" in this bit.
This bit is set to 1 at the following times:
(1) Single mode: when one A/D conversion is completed.
(2) Scan mode: when inputs on all selected channels have
been converted.
(Initial value)
Bit 6 – A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI)
when A/D conversion is completed.
Bit 6
ADIE
0
1
Description
The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
(Initial value)
Bit 5 – A/D Start (ADST): The A/D converter operates while this bit is set to “1.” In the single
mode, this bit is automatically cleared to “0” at the end of each A/D conversion.
Bit 5
ADST
0
1
Description
A/D conversion is halted.
(Initial value)
(1) Single mode: One A/D conversion is performed. The ADST
bit is automatically cleared to “0” at the end of the conversion.
(2) Scan mode: A/D conversion starts and continues cyclically on the selected
channels until the ADST bit is cleared to “0” by software (or a reset, or by entry to
a standby mode).
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