HD6433308 Datasheet, PDF (172/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 2
CKS2
0
0
0
0
1
1
1
1
Bit 1
CKS1
0
0
1
1
0
0
1
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
No clock source (timer stopped)
(Initial value)
Ø/8 Internal clock source, counted on the falling edge
Ø/64 Internal clock source, counted on the falling edge
Ø/1024 Internal clock source, counted on the falling edge
No clock source (timer stopped)
External clock source, counted on the rising edge
External clock source, counted on the falling edge
External clock source, counted on both the rising
and falling edges
7.2.4 Timer Control/Status Register (TCSR) – H’FFC9 (TMR0), H’FFD1 (TMR1)
Bit
7
6
5
4
CMFB CMFA OVF —
Initial value
0
0
0
1
Read/Write R/(W)* R/(W)* R/(W)* —
3
2
1
0
OS3 OS2 OS1 OS0
0
0
0
0
R/W R/W R/W R/W
* Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H’10 at a reset and in the standby modes.
Bit 7 – Compare-Match Flag B (CMFB): This status flag is set to “1” when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7
CMFB
0
1
Description
To clear CMFB, the CPU must read CMFB after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORB.
(Initial value)
Bit 6 – Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
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