HD6433308 Datasheet, PDF (217/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 9-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur
Receive error
Overrun error
Framing error
Parity error
Overrun + framing errors
Overrun + parity errors
Framing + parity errors
Overrun + framing + parity errors
RDRF
1*¹
0
0
1*¹
1*¹
0
1*¹
SSR Bits
ORER
1
0
0
1
1
0
1
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
RSR → RDR*²
No
Yes
Yes
No
No
Yes
No
*¹ Set to “1” before the overrun error occurs.
*² Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
(3) Line Break Detection: When the ARxD pin receives a continuous stream of 0’s in the
asynchronous mode (line-break state), a framing error occurs because the SCI detects a “0” stop bit.
The value H’00 is transferred from the RSR to the RDR. Software can detect the line-break state as
a framing error accompanied by H’00 data in the RDR.
The SCI continues to receive data, so if the FER bit is cleared to “0” another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by
the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is
detected by sampling the ARxD input on the falling edge of this clock. After the start bit is
detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits)
is sampled on the rising edge of the serial clock pulse at the center of the bit. See Figure 9-6.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data
can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
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