HD6433308 Datasheet, PDF (262/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Section 14. Power-Down State
14.1 Overview
The H8/330 has a power-down state that greatly reduces power consumption by stopping some or
all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 14-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 14-1. Power-Down State
Mode
Sleep
mode
Soft-
ware
standby
mode
Hard-
ware
standby
mode
Entering
procedure
Clock
Execute
Run
SLEEP
instruction
Set SSBY bit Halt
in SYSCR to
“1,” then
execute SLEEP
instruction
Set STBY
Halt
pin to Low
level
CPU
Halt
Halt
Halt
CPU Sup.
Reg’s. Mod.* RAM
Held Run Held
Held Halt Held
and
initial-
ized
I/O
ports
Held
Held
Exiting
methods
• Interrupt
• RES
• STBY
• NMI
• IRQ0 – IRQ2
• STBY
• RES
Not Halt Held High • STBY High,
held and
impe- then RES
initialized
dance Low → High
state
Notes
1. SYSCR: System control register
2. SSBY: Software standby bit
3. On-chip supporting modules, including the dual-port RAM.
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