HD6433308 Datasheet, PDF (347/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Appendix D. Timing of Transition to and Recovery From
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1). To retain RAM contents, drive the RES signal low 10 system clock cycles before the STBY
signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay
from STBY low to RES high: 0 ns).
STBY
RES
t₁ ≥ 10 t_cyc
t₂ ≥ 0 ns
(2). When it is not necessary to retain RAM contents, RES does not have to be driven low as in
(1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t = 100 ns
t _OSC
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