HD6433308 Datasheet, PDF (241/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

11.2.2 Parallel Communication Data Register 0 (PCDR0) – H’FFF1
(a) Parallel Communication Data Register 0A (PCDR0A)
Bit
7
6
5
4
3
2
1
0
Initial value
—
—
—
—
—
—
—
—
R/W H8/300 CPU R
R
R
R
R
R
R
R
Master CPU W
W
W
W
W
W
W
W
(b) Parallel Communication Data Register 0B (PCDR0B)
Bit
7
6
5
4
3
2
1
0
Initial value
—
—
—
—
—
—
—
—
R/W H8/300 CPU W
W
W
W
W
W
W
W
Master CPU R
R
R
R
R
R
R
R
Parallel communication data register 0 consists of two separate 8-bit registers with the same
address. As shown in Figure 11-2, PCDR0A is written by the H8/300 CPU and read by the master
CPU; PCDR0B is written by the master CPU and read by the H8/300 CPU. This arrangement
prevents contention even if both CPUs write to PCDR0 at the same time. When either CPU reads
PCDR0, it is assured of reading data written by the other CPU.
Internal data bus
Read
Write
H8/300 CPU
PCDR0A
PCDR0B
Write
External data bus
Read
PCDR 0
Master CPU
Figure 11-2. Parallel Communication Data Register 0
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