HD6433308 Datasheet, PDF (83/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Interrupt
accepted
Interrupt priority
decision. Wait for Instruction Internal
end of instruction. fetch
process-
ing
Interrupt request
signal
Stack
Vector
table
fetch
Instruction fetch
(first instruction of
Internal interrupt-handling
process- routine)
ing
Ø
Internal address
bus
Internal Read
signal
Internal Write
signal
(1)
(3)
(5)
(6)
(8)
(9)
Internal 16-bit
data bus
(2)
(4)
(1)
(7)
(9)
(10)
(1) Instruction prefetch address (Pushed on stack. Instruction is executed on return from
((12₍))_{2()4)(4iInIn)}ntsestrtrrr_{iIuuunncpctste}tti_ti-o_rroh_runnauccnpp_toditr_{o-delihnnefeagc}t(_ncNr_oohdodulat_ietnideng(dxe_{Nerr.e)oocsuut}st_teei(_nxdPee)u.cs_)uh_te_ed_do₎ n stack. Instruction is executed on return from
(3⁽)³⁾ Instr^Iuⁿc^st^tio^run^cp^tir^oeⁿfet^pc^rh^ea^fed^td^cr^hes^as^d(^dN^ro^et^se^sx⁽e^Ncu^ot^te^ed^x) ^ecuted)
(5⁽)⁵⁾ SP–2^SP–2
(6⁽)⁶⁾ SP–4^SP–4
(7()7) CCRCCR
(8()8) AddrAedssdroefsvsecotforvteacbtloeretnatbryle entry
(9()9) VectVoer ctatoblretaebntlrey e(andtrdyre(sasdodfrefirssst oinfsftirusct tinosntirnutcetrirounpti-nhtaenrdrulinpgt-rhoauntidnelin) g routine)
(1₍0₁)₀₎ First_Fin_irs_st_tru_inc_stio_trn_uco_tf_ioin_nte_orr_fu_ip_nt_t-_eh_ra_rn_ud_pli_tn_-hg_aro_nu_dt_li_in_ne_{g routine}
Figure 4-5. Timing of Interrupt Sequence
68