HD6433308 Datasheet, PDF (31/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 1-3. Pin Functions (2)
Type
Symbol I/O
Data bus D7 to D0 I/O
Bus
WAIT I
control
RD
O
WR
O
AS
O
IOS
O
Interrupt NMI
I
signals
IRQ0 to I
IRQ7
Operating MD1, I
mode
MD0
control
Name and function
Data bus: 8-Bit bidirectional data bus.
Wait: Requests the CPU to insert TW states into the bus cycle
when an off-chip address is accessed.
Read: Goes Low to indicate that the CPU is reading an external
address.
Write: Goes Low to indicate that the CPU is writing to an
external address.
Address Strobe: Goes Low to indicate that there is a valid
address on the address bus.
I/O Select: Goes Low when the CPU accesses addresses H’FF00
to H’FFFF. Can be used as a chip select signal replacing the upper
8 bits of the address bus when external devices are mapped onto
addresses H’FF80 to H’FF8F and H’FFA8 to H’FFAF.
NonMaskable Interrupt: Highest-priority interrupt request.
The NMIEG bit in the system control register determines whether
the interrupt is requested on the rising or falling edge of the NMI
input.
Interrupt Request 0 to 7: Maskable interrupt request pins.
Mode: Input pins for setting the MCU operating mode
according to the table below.
MD1 MD0
0
1
1
0
1
1
Mode
Mode 1
Mode 2
Mode 3
Description
Expanded mode with
on-chip ROM disabled
Expanded mode with
on-chip ROM enabled
Single-chip mode
The inputs at these pins are latched in mode select bits 1 to 0
(MDS1 and MDS0) of the mode register (MDCR) on the rising
edge of the RES signal.
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