HD6433308 Datasheet, PDF (84/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

4.2.1 Interrupt-Related Registers
The interrupt controller refers to three registers in addition to the CCR. The names and attributes of
these registers are listed in Table 4-3.
Table 4-3. Registers Read by Interrupt Controller
Name
System control register
IRQ sense control register
IRQ enable register
Abbreviation
SYSCR
ISCR
IER
Read/write
R/W
R/W
R/W
Address
H’FFC4
H’FFC6
H’FFC7
(1) System Control Register (SYSCR)—H’FFC4
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
0
— NMIEG DPME RAME
1
0
0
1
—
R/W R/W R/W
The first four bits of the system control register concern the software standby mode, and the last
two bits enable the on-chip RAM and dual-port RAM. Bit 2 is the only bit read by the interrupt
controller.
Bit 2—Nonmaskable Interrupt Edge (NMIEG): This bit determines whether a nonmaskable
interrupt is generated on the falling or rising edge of the NMI input signal.
Bit 2
NMIEG
0
1
Description
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
(2) IRQ Sense Control Register (ISCR)—H’FFC6
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
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