HD6433308 Datasheet, PDF (222/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

10.2 Register Descriptions
10.2.1 A/D Data Registers (ADDR) – H’FFE0 to H'FFE6
Bit
7
6
5
4
3
2
1
0
ADDRn
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results
of A/D conversion. Each data register is assigned to two analog input channels as indicated in
Table 10-3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H’00 at a reset and in the standby modes.
Table 10-3. Assignment of Data Registers to Analog Input Channels
Analog input channel
Group 0 Group 1 A/D data register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
10.2.2 A/D Control/Status Register (ADCSR) – H’FFE8
Bit
7
6
5
4
3
2
1
0
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W
* Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
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