HD6433308 Datasheet, PDF (104/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Port 4 Data Register (P4DR)—H’FFB7
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
P4DR is an 8-bit register containing the data for pins P47 to P40. When the CPU reads P4DR, for
output pins (P4DDR = "1") it reads the value in the P4DR latch, but for input pins (P4DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies to pins
used for timer input or output.
MOS Pull-Ups: Are available for input pins, including timer input pins, in all modes. Software
can turn the MOS pull-up on by writing a “1” in P4DR, and turn it off by writing a “0.”
Pins P40, P42, P43, and P45: As indicated in Table 5-8, these pins can be used for general-purpose
input or output, or input of 8-bit timer clock and reset signals. When a pin is used for timer signal
input, its P4DDR bit should normally be cleared to "0;" otherwise the timer will receive the value
in P4DR. If input pull-up is not desired, the P4DR bit should also be cleared to "0."
Pins P41, P44, P46, and P47: As indicated in Table 5-8, these pins can be used for general-purpose
input or output, or for 8-bit timer output (P41 and P44) or PWM timer output (P46 and P47). Pins
used for timer output are unaffected by the values in P4DDR and P4DR, and their MOS pull-ups
are automatically turned off.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P4DDR and P4DR to all “0” and makes all pins into input port pins with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, the control registers of the 8-bit and
PWM timers are initialized but P4DDR and P4DR remain in their previous states. All pins become
input or output port pins depending on the setting of P4DDR. Output pins output the values in
P4DR. The MOS pull-ups of input pins are on or off depending on the values in P4DR.
Figures 5-4 and 5-5 show schematic diagrams of port 4.
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