HD6433308 Datasheet, PDF (226/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

H'FF
H'00
AVss
AVcc
Figure 10-2. The Response of the A/D Converter
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
10.3.1 Single Mode (SCAN = 0)
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to “1,” either by software or by a High-to-Low
transition of the ADTRG signal (if enabled). During the conversion process the ADST bit remains
set to “1.” When conversion is completed, the ADST bit is automatically cleared to “0.”
When the conversion is completed, the ADF bit is set to “1.” If the interrupt enable bit (ADIE) is
also set to “1,” an A/D conversion end interrupt (ADI) is requested, so that the converted data can
be processed by an interrupt-handling routine. The ADF bit is cleared when software reads the
A/D control/status register (ADCSR), then writes a “0” in this bit.
Before selecting the single mode, clock, and analog input channel, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
when the ADST bit is set to "1" again. The same instruction can be used to alter the mode and
channel selection and set ADST to "1."
214