HD6433308 Datasheet, PDF (21/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

1.2 Descriptions of Blocks
CPU: The CPU has a high-speed-oriented architecture in which operands are located in general registers.
• Two-way general register configuration
- Eight 16-bit registers, or
- Sixteen 8-bit registers
• Streamlined instruction set
- Instruction length: 2 or 4 bytes
- Register-register arithmetic, logic, and shift operations, including:
- 8 × 8-bit multiply
- 16 ÷ 8-bit divide
- Extensive bit-manipulation instructions, featuring:
- Bit accumulator
- Register-indirect specification of bit positions
- Maximum clock rate: 10MHz
- Register-register add or subtract: 0.2µs
- Register-register multiply or divide: 1.4µs
ROM: The 16K-byte on-chip ROM is accessed in two states via a 16-bit bus. Three versions are
available:
• Masked ROM
• Electrically programmable ROM, programmable with a standard PROM writer
• No ROM
RAM: The 512-byte on-chip RAM is accessed in two states via a 16-bit bus. RAM contents are
held in the power-down state.
Dual-Port RAM: In single-chip mode, the 15 bytes of dual-port memory can be accessed by both
the on-chip CPU and an external CPU for convenient parallel data transfer in master-slave systems.
Serial Communication Interface: The single serial I/O channel offers:
• Synchronous or asynchronous communication
• Separate input/output pins for the synchronous and asynchronous modes
• An on-chip baud rate generator supporting up to megabit-per-second speeds
• Serial clock input or output
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