HD6433308 Datasheet, PDF (318/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

TCSR—Timer Control/Status Register
H’FF91
FRT
Bit
7
6
ICFA ICFB
Initial value 0
0
Read/Write R/(W)* R/(W)*
5
ICFC
0
R/(W)*
4
3
2
1
0
ICFD OCFA OCFB OVF CCLRA
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/W
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when FRC changes from H’FFFF to H’0000.
Output Compare Flag B
0 Cleared when CPU reads OCFB = “1”, then writes “0” in OCFB.
1 Set when FRC = OCRB.
Output Compare Flag A
0 Cleared when CPU reads OCFA = “1”, then writes “0” in OCFA.
1 Set when FRC = OCRA.
Input Capture Flag D
0 Cleared when CPU reads ICFD = “1”, then writes “0” in ICFD.
1 Set by FTID input.
Input Capture Flag C
0 Cleared when CPU reads ICFC = “1”, then writes “0” in ICFC.
1 Set by FTIC input.
Input Capture Flag B
0 Cleared when CPU reads ICFB = “1”, then writes “0” in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0 Cleared when CPU reads ICFA = “1”, then writes “0” in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
* Software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these bits
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