HD6433308 Datasheet, PDF (300/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Appendix B. Instruction Set List (cont.)
Mnemonic
Operation
Addressing mode/
instruction length
Condition code
SHAL.B Rd
C
B
b7
0
2
b0
I H N ZV C
– – ◊◊ ◊ ◊ 2
SHAR.B Rd
B
C
2
– – ◊◊ 0 ◊ 2
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
b7
B_C
b7
B₀
b7
BC
b0
0
2
b0
C
2
b0
0
2
– – ◊◊ 0 ◊ 2
– – 0◊ 0 ◊ 2
– – ◊◊ 0 ◊ 2
ROTXR.B Rd
b7
B
b0
C
2
– – ◊◊ 0 ◊ 2
ROTL.B Rd
ROTR.B Rd
b7
B_C
b7
B
b0
0
2
b0
C
2
– – ◊◊ 0 ◊ 2
– – ◊◊ 0 ◊ 2
b7
b0
BSET #xx:3,Rd
B (#xx:3 of Rd8) ← 1
2
– – –– – – 2
BSET #xx:3,@Rd
B (#xx:3 of @Rd16) ← 1
4
– – –– – – 8
BSET #xx:3,@aa:8
B (#xx:3 of @aa:8) ← 1
4
– – –– – – 8
BSET Rn,Rd
B (Rn8 of Rd8) ← 1
2
– – –– – – 2
BSET Rn,@Rd
B (Rn8 of @Rd16) ← 1
4
– – –– – – 8
BSET Rn,@aa:8
B (Rn8 of @aa:8) ← 1
4
– – –– – – 8
BCLR #xx:3,Rd
B (#xx:3 of Rd8) ← 0
2
– – –– – – 2
BCLR #xx:3,@Rd
B (#xx:3 of @Rd16) ← 0
4
– – –– – – 8
BCLR #xx:3,@aa:8
B (#xx:3 of @aa:8) ← 0
4
– – –– – – 8
BCLR Rn,Rd
B (Rn8 of Rd8) ← 0
2
– – –– – – 2
BCLR Rn,@Rd
B (Rn8 of @Rd16) ← 0
4
– – –– – – 8
BCLR Rn,@aa:8
B (Rn8 of @aa:8) ← 0
4
– – –– – – 8
BNOT #xx:3,Rd
B (#xx:3 of Rd8) ← (#xx:3 of Rd8)
2
– – –– – – 2
BNOT #xx:3,@Rd
B (#xx:3 of @Rd16) ←(#xx:3 of @Rd16)
4
– – –– – – 8
BNOT #xx:3,@aa:8
B (#xx:3 of @aa:8) ← (#xx:3 of @aa:8)
4
– – –– – – 8
292