HD6433308 Datasheet, PDF (141/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 6-2. Register Configuration (cont.)
Name
Input capture register B (High)
Input capture register B (Low)
Input capture register C (High)
Input capture register C (Low)
Input capture register D (High)
Input capture register D (Low)
Abbreviation
ICRB (H)
ICRB (L)
ICRC (H)
ICRC (L)
ICRD (H)
ICRD (L)
R/W
R
R
R
R
R
R
value
H’00
H’00
H’00
H’00
H’00
H’00
Initial
Address
H’FF9A
H’FF9B
H’FF9C
H’FF9D
H’FF9E
H’FF9F
6.2 Register Descriptions
6.2.1 Free-Running Counter (FRC) – H’FF92
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
When the FRC overflows from H’FFFF to H’0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written
or read. See section 6.3, “CPU Interface” for details.
The FRC is initialized to H’0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.
126