HD6433308 Datasheet, PDF (85/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bits 0 to 7 – IRQ0 to IRQ7 Sense Control (IRQ0SC to IRQ7SC): These bits determine whether
the IRQ0 to IRQ7 inputs are edge-sensed or level-sensed.
Bit i
IRQiSC
0
1
Description
IRQi is level-sensed.
IRQi is sensed on the falling edge.
(Initial state)
Edge-sensed interrupt signals are latched (if enabled) until the interrupt is serviced. They are
latched even if the interrupt mask bit (I) is set in the CCR, and remain latched even if the enable bit
(IRQ0E to IRQ7E) is later cleared to 0.
(3) IRQ Enable Register (IER)—H’FFC7
Bit
Initial value
Read/Write
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
Bits 0 to 7 – IRQ0 to IRQ7 Enable (IRQ0E to IRQ7E): These bits enable or disable the IRQi
signals individually.
After a reset, all IRQi interrupts are disabled (as well as masked).
Bit i
IRQiE
0
1
Description
IRQi is disabled.
IRQi is enabled.
(Initial state)
4.2.2 External Interrupts
The external interrupts are NMI and IRQ0 to IRQ7.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register.
An NMI has highest priority and is always accepted as soon as the current instruction ends, unless
the current instruction is an ANDC, ORC, XORC, or LDC instruction. When an NMI interrupt is
70