HD6433308 Datasheet, PDF (59/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Before Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
Pull-up Mos
P47
Input
Low
0
1
On
P46
Input
High
0
0
Off
P45 P44 P43 P42 P41 P40
Output Output Output Output Output Output
Low Low Low Low Low Low
1
1
1
1
1
1
0
0
0
0
0
0
Off Off Off Off Off Off
Execution of BCLR Instruction
BCLR.B #0, @P4DDR
;clear bit 0 in data direction register
After Execution of BCLR Instruction
P47 P46 P45 P44 P43 P42 P41 P40
Input/output Output Output Output Output Output Output Output Input
Pin state
Low High Low Low Low Low Low High
DDR
1
1
1
1
1
1
1
0
DR
1
0
0
0
0
0
0
0
Pull-up Mos Off Off Off Off Off Off Off Off
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to "0," making P40 an input pin. In addition, P47DDR and P46DDR
are set to "1," making P47 and P46 output pins.
Example 2: BSET is executed to set bit 0 in the port 4 data register (P4DR) under the following
conditions.
P47:
Input pin, Low, MOS pull-up transistor on
P46:
Input pin, High, MOS pull-up transistor off
P45 – P40: Output pins, Low
The intended purpose of this BSET instruction is to switch the output level at P40 from Low to
High.
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