HD6433308 Datasheet, PDF (343/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

PCCSR—Parallel Communication Control/Status Register H’FFF0
DPRAM
Bit
7
MWEF
Initial value 0
Read/Write
H8/300 CPU: R
Master CPU: R
6
EMWI
0
R/W
R
5
4
3
SWEF EAKAR MREF
0
0
0
R
R/W R
R
R/W R
2
EMRI
0
R/W
R
1
0
MWMF SWMF
0
0
R
R
R
R
Master Write End Flag
0 H8/300 CPU has read PCDR14 while MWMF = "1."
1 Master CPU has written data in PCDR14.
Enable Master Write Interrupt
0 Master write end interrupt (MWEI) is disabled.
1 Master write end interrupt (MWEI) is enabled.
Slave Write End Flag
0 Master CPU has read PCDR14.
1 H8/300 CPU has written data in PCDR14.
Enable Acknowledge and Request
0 RDY output is disabled. Remains in high-impedance state.
1 RDY output is enabled.
Master Read End Flag
0 Cleared when H8/300 CPU reads or writes
PCDR0, or master CPU writes to PCDR0.
1 Set when master CPU reads PCDR0.
Enable Master Read Interrupt
0 Master read end interrupt (MREI) is disabled.
1 Master read end interrupt (MREI) is enabled.
Master Write Mode Flag
0 Not master write mode. Cleared when H8/300 CPU reads PCDR0.
1 Master write mode. Set if the master CPU writes to PCDR0 while
SWMF = “0.”
Slave Write Mode Flag
0 Not slave write mode. Cleared when master CPU reads
PCDR0.
1 Slave write mode. Set if H8/300 CPU writes to PCDR0
while MWMF = “0.”
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