HD6433308 Datasheet, PDF (150/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Bit 5 – Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on
the selected edge of the input capture C signal (FTIC). In buffer mode (when BUFEA = “1”),
it also causes input capture A events to be recognized on the selected edge of FTIA.
Bit 5
IEDGC
0
1
Description
Input capture C events are recognized on the falling edge of FTIC.
Input capture C events are recognized on the rising edge of FTIC.
(Initial value)
Bit 4 – Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on
the selected edge of the input capture D signal (FTID). In the buffer mode (when BUFEB = “1”),
it also causes input capture B events to be recognized on the selected edge of FTIB.
Bit 4
IEDGD
0
1
Description
Input capture D events are recognized on the falling edge of FTID.
Input capture D events are recognized on the rising edge of FTID.
(Initial value)
Bit 3 – Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA
0
1
Description
ICRC is used for input capture C.
(Initial value)
ICRC is used as a buffer register for input capture A. Input C is not captured.
Bit 2 – Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB
0
1
Description
ICRD is used for input capture D.
(Initial value)
ICRD is used as a buffer register for input capture B. Input D is not captured.
Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
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