HD6433308 Datasheet, PDF (196/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The TDR is initialized to H’FF at a reset and in the standby modes.
9.2.5 Serial Mode Register (SMR) – H’FFD8
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
C/A CHR PE
O/E STOP — CKS1 CKS0
0
0
0
0
0
1
0
0
R/W R/W R/W R/W R/W
—
R/W R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H’04 at a reset and in the standby
modes.
Bit 7 – Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
0
1
Description
Asynchronous communication.
Clock-synchronized communication.
(Initial value)
Bit 6 – Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR Description
0 8 Bits per character.
1 7 Bits per character.
(Initial value)
Bit 5 – Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE Description
0 Transmit: No parity bit is added.
Receive: Parity is not checked.
1 Transmit: A parity bit is added.
Receive: Parity is checked.
(Initial value)
183