HD6433308 Datasheet, PDF (238/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

11.1.3 Input and Output Pins
Table 11-1 lists the input and output pins of the dual-port RAM.
Table 11-1. Dual-Port RAM Input and Output Pins
Name
DPRAM data bus
Abbreviation
DDB7 to DDB0
Chip select
Register select
Output enable
Write enable
Ready
CS
RS3 to RS0
OE
WE
RDY
* NMOS open drain output.
I/O
Function
Input/output An 8-bit parallel data bus by which the
master CPU can access the dual-port
RAM.
Input
Chip select input pin for selecting the
dual-port RAM.
Input
Dual-port RAM address input.
Input
Enables output on the DPRAM data bus.
Input
Enables data to be written in the dual-port
RAM via the DPRAM data bus.
Output * Indicates that the dual-port RAM is ready
to be written or read by the master CPU.
(NMOS open-drain output)
11.1.4 Register Configuration
Table 11-2 lists the registers of the dual-port RAM.
Table 11-2. Dual-Port RAM Register Configuration
Read/write
H8/300 Master Initial On-chip External address
Name
Abbr. CPU CPU value address RS3 RS2 RS1 RS0
Parallel communication PCCSR R/(W)* R/(W)* H’00 H’FFF0 0 0 0 0
control/status register
Parallel communication PCDR0A R
W
Undeter- H’FFF1 0 0 0 1
data register 0
PCDR0B W
R
mined H’FFF1 0 0 0 1
Parallel communication PCDR1 R/W R/W Undeter- H’FFF2 0 0 1 0
data register 1
mined
Parallel communication PCDR2 R/W R/W Undeter- H’FFF3 0 0 1 1
data register 2
mined
Parallel communication PCDR3 R/W R/W Undeter- H’FFF4 0 1 0 0
data register 3
mined
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