HD6433308 Datasheet, PDF (14/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

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Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Block Diagram ...................................................................................................... 2
Pin Arrangement (FP-80A, Top View) ................................................................. 6
Pin Arrangement (CP-84, Top View) .................................................................... 7
Pin Arrangement (CG-84, Top View) ................................................................... 8
Figure 2-1 Address Space Map............................................................................................... 20
Figure 3-1 CPU Registers ....................................................................................................... 26
Figure 3-2 Stack Pointer ......................................................................................................... 27
Figure 3-3 Register Data Formats........................................................................................... 32
Figure 3-4 Memory Data Formats .......................................................................................... 33
Figure 3-5 Data Transfer Instruction Codes............................................................................ 37
Figure 3-6 Arithmetic, Logic, and Shift Instruction Codes .................................................... 40
Figure 3-7 Bit Manipulation Instruction Codes ...................................................................... 46
Figure 3-8 Branching Instruction Codes................................................................................. 48
Figure 3-9 System Control Instruction Codes......................................................................... 50
Figure 3-10 Block Data Transfer Instruction/EEPROM Write Operation Code ...................... 51
Figure 3-11 Operating States .................................................................................................... 51
Figure 3-12 State Transitions .................................................................................................... 52
Figure 3-13 On-Chip Memory Access Cycle ........................................................................... 54
Figure 3-14 Pin States during On-Chip Memory Access Cycle ............................................... 54
Figure 3-15 On-Chip Register Field Access Cycle................................................................... 55
Figure 3-16 Pin States during On-Chip Register Field Access Cycle ...................................... 56
Figure 3-17(a) External Device Access Timing (read) ................................................................. 56
Figure 3-17(b) External Device Access Timing (write) ................................................................ 57
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Reset Sequence (Mode 2 or 3, Reset Routine in On-Chip ROM)......................... 61
Reset Sequence (Mode 1)...................................................................................... 62
Block Diagram of Interrupt Controller.................................................................. 66
Hardware Interrupt-Handling Sequence................................................................ 67
Timing of Interrupt Sequence................................................................................ 68
Usage of Stack in Interrupt Handling.................................................................... 74
Example of Damage Caused by Setting an Odd Address in R7 ........................... 75
Example of Deferred Interrupt .............................................................................. 76
Figure 5-1 Port 1 Schematic Diagram..................................................................................... 81
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