HD6433308 Datasheet, PDF (90/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

PC _H
SP
PC _L
SP
R1 _L
H'FFCC
PC L
H'FFCD
SP
H'FFCF
BSR instruction
MOV.B R1L, @–R7
H'FFCF set in SP
PC is improperly stored
beyond top of stack
PC His lost
PC_H: Upper byte of program counter
PCL : Lower byte of program counter
R1L : General register
SP : Stack pointer
Figure 4-7. Example of Damage Caused by Setting an Odd Address in R7
4.2.6 Deferring of Interrupts
As noted previously, no interrupt is accepted immediately after a reset. System control instructions
that rewrite the CCR have a similar effect. Interrupts requests received during one of these
instructions are deferred until at least one more instruction has been executed.
The instructions that defer interrupts in this way are XORC, ORC, ANDC, and LDC. At the
completion of these instructions the interrupt controller does not check the interrupt signals. The
CPU therefore always proceeds to the next instruction. (And if the next instruction is one of these
four, the CPU also proceeds to the next instruction after that.) The interrupt-handling sequence
starts after the next instruction that is not one of these four has been executed. Figure 4-8 shows an
example.
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