HD6433308 Datasheet, PDF (101/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The MOS pull-ups cannot be used in slave mode (when the dual-port RAM is enabled). P3DR
should be cleared to H'00 (its initial value) in slave mode.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values
in P3DDR and P3DR are ignored.
Mode 3: In the single-chip mode, when the dual-port RAM enable (DPME) bit in the system
control register is cleared to “0,” port 3 can be used as a general-purpose input/output port.
When DPME is set to “1,” entering the slave mode, port 3 is used as the dual-port RAM data bus
(DDB7 to DDB0). P3DR should also be cleared to H'00 in slave mode.
See section 12, “Dual-Port RAM” for further information.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P3DDR and P3DR to all “0,” and clears the DPME bit to "0." In modes 1 and 2, all pins are placed
in the data input (high-impedance) state. In mode 3 (single-chip mode), all pins are in the input
state with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, P3DDR, P3DR, and the DPME bit
remain in their previous state. In modes 1 and 2 and slave mode, all pins are placed in the data
input (high-impedance) state. In mode 3 with the dual-port RAM disabled, all pins remain in their
previous input or output state.
Figure 5-3 shows a schematic diagram of port 3.
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