HD6433308 Datasheet, PDF (242/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

The value in PCDR0 after a reset is undetermined. In non-slave modes, the value obtained by
reading PCDR0 is unpredictable.
11.2.3 Parallel Communication Data Registers 1 to 14 – H’FFF2 (PCDR1) to H’FFFF
(PCDR1-14)
Bit
7
6
5
4
3
2
1
0
Initial value
—
—
—
—
—
—
—
—
R/W H8/300 CPU R/W R/W R/W R/W R/W R/W R/W R/W
Master CPU R/W R/W R/W R/W R/W R/W R/W R/W
Parallel communication data registers 1 to 14 are 8-bit registers which can be written and read by
either the H8/300 CPU or the master CPU. The H8/300 CPU can read and write these registers
regardless of the operating mode of the H8/330 chip. The master CPU can read and write them
only when the H8/330 chip is operating in slave mode.
In non-slave modes, these registers can be used as 14 bytes of data memory. Note that access
requires three states per byte, which is slower than the on-chip RAM.
The values in PCDR1 to PCDR14 after a reset are undetermined.
11.2.4 Parallel Communication Control/Status Register (PCCSR) – H’FFF0
Bit
7
MWEF
Initial value
0
R/W H8/300 CPU R
Master CPU R
6
EMWI
0
R/W
R
5
SWEF
0
R
R
4
EAKAR
0
R/W
R/W
3
MREF
0
R
R
2
EMRI
0
R/W
R
1
0
MWMF SWMF
0
0
R
R
R
R
The PCCSR is an 8-bit readable and partly writable register that provides protocol and interrupt
control functions. Either CPU can read and write bit 4, which enables the RDY signal. The
H8/300 CPU can read and write bits 6, 4 and 2, which enable interrupts. The other bits are read-
only bits.
The PCCSR is initialized to H’00 at a reset and in the standby modes.
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