HD6433308 Datasheet, PDF (74/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Section 4. Exception Handling
As indicated in table 4-1, the H8/330 recognizes only two kinds of exceptions: interrupts (28
sources) and the reset. There are no error or trap exceptions.
When an exception occurs the CPU enters the exception-handling state and performs a hardware
exception-handling sequence. There are two exception-handling sequences: one for the reset and
one for interrupts. In both sequences the CPU:
• Sets the interrupt mask (I) bit in the CCR to “1,” and
• Loads the program counter (PC) from the vector table.
After the program counter is loaded, the CPU returns to the program execution state and program
execution starts from the new PC address.
The vector table occupies addresses H’0000 to H’003D in memory. It consists of word entries
giving the addresses of software interrupt-handling routines and the reset routine. The entries are
indexed by a vector number associated with the particular exception.
For an interrupt, before the PC and CCR are altered as described above, the old PC and CCR
contents are pushed on the stack, so that they can be restored when an RTE (Return from
Exception ) instruction is executed.
If a reset and interrupt occur simultaneously, the reset has priority. There is also a priority order
among different types of interrupts. Table 4-1 compares the reset and interrupt exceptions.
Table 4-1. Reset and Interrupt Exceptions
Item
Priority
Cause
When detected
Reset
Highest
Low RES input
Any clock period
When handled
Vector numbers
Vector table
Immediately
0
H’0000 – H’0001
Interrupt
Lower
Internal or external interrupt signal
At end of current instruction, unless current
instruction is ANDC, ORC, XORC, or LDC, or at
end of hardware interrupt-handling sequence.
At end of current instruction.
3 to 30
H’0006 – H’003D
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