HD6433308 Datasheet, PDF (243/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

In the bit names that follow, the H8/300 is referred to as the slave and the master CPU as the
master.
Bit 7 – Master Write End Flag (MWEF): This flag bit is used to indicate that the master CPU
has finished writing data in the parallel communication data registers. It is set when the master
CPU writes to PCDR14 and cleared when the H8/300 CPU reads PCDR14.
Bit 7
MWEF
0
1
Description
The H8/300 CPU has read PCDR14 while the dual-port
RAM was in the master write mode (MWMF = "1").
The master CPU has written data in PCDR14.
(Initial state)
Bit 6 – Enable Master Write Interrupt (EMWI): This bit enables or disables the master write
end interrupt (MWEI).
Bit 6
EMWI
0
1
Description
The master write end interrupt request (MWEI) is disabled.
The master write end interrupt request (MWEI) is enabled.
(Initial state)
Bit 5 – Slave Write End Flag (SWEF): This flag bit is used to indicate that the H8/300 CPU has
finished writing data in the parallel communication data registers. It is set when the H8/300 CPU
writes to PCDR14 and cleared when the master CPU reads PCDR14.
Bit 5
SWEF
0
1
Description
The master CPU has read PCDR14.
The H8/300 CPU has written data in PCDR14.
(Initial state)
Bit 4 – Enable Acknowledge and Request (EAKAR): This bit enables or disables the RDY
signal output by the H8/330 chip. If enabled:
• The RDY signal goes Low when the H8/300 CPU reads PCDR0 while the dual-port RAM is in
the master write mode (MWMF = "1"), or when the H8/300 CPU writes to PCDR14.
• The RDY signal goes High when the master CPU reads PCDR14 or the PCCSR, or when either
the master or H8/300 CPU writes to PCDR0.
In the non-slave modes this bit has no effect.
232