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HD6433308 Datasheet, PDF (46/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer | |||
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(6) Immediateâ#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or
a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the
instruction, specifying a bit number.
(7) PC-Relativeâ@(d:8, PC): This mode is used to generate branch addresses in the Bcc and
BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended value
to the program counter contents. The result must be an even number. The possible branching
range is â126 to +128 bytes (â63 to +64 words) from the current address.
(8) Memory Indirectâ@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from Hâ0000 to Hâ00FF (0 to
255). The word located at this address contains the branch address. Note that addresses Hâ0000 to
Hâ003D (0 to 61) are located in the vector table.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as â0,â causing word access to be performed at the
address preceding the specified address. See section 3.4.2, âMemory Data Formatsâ for further
information.
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