HD6433308 Datasheet, PDF (88/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

Table 4-4. Number of States before Interrupt Service
No. Reason for wait
1 Interrupt priority decision
2 Wait for completion of
current instruction (note 1)
3 Save PC and CCR
4 Fetch vector
5 Fetch instruction
6 Internal processing
Total
Number of states
On-chip memory External memory
2 (note 3)
2 (note 3)
1 to 13
5 to 17 (note 2)
4
2
4
4
17 to 29
12 (note 2)
6 (note 2)
12 (note 2)
4
41 to 53 (note 2)
Notes:
1. These values do not apply if the current instruction is an EEPMOV, MOVFPE, or
MOVTPE instruction.
2. If wait states are inserted in external memory access, these values may be longer.
3. 1 for internal interrupts.
4.2.5 Note on Stack Handling
When the H8/330 performs word access, the least significant bit of the address is always assumed
to be “0.” If an odd address is specified, no address error occurs, but the intended address is not
accessed.
The stack is always accessed by word access. Care should be taken to keep an even value in the
stack pointer (general register R7). The PUSH and POP (or MOV.W Rn, @–SP and MOV.W
@SP+, Rn) instructions should be used for pushing and popping registers on the stack. The
MOV.B Rn, @–SP and MOV.B @SP+, Rn instructions should never be used; they can easily cause
programs to crash.
Figure 4-6 shows how the PC and CCR are pushed on the stack during the hardware interrupt-
handling sequence. The CCR is saved as a word consisting of two identical bytes, both containing
the CCR value. On return from the interrupt-handling routine, the CCR is popped from the upper
of these two bytes. The lower byte is ignored.
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